Recent advancement of design technologies has enabled development of increasingly large-scale software and hardware products. To pursue the design process while ensuring that the product under development will work as it is intended, the stage of design and development involves design verification. This verification task is becoming more and more part of a development process because of the increasing scale of target products as noted above. The deadline of a development project, on the other hand, may sometimes be moved up, and the actual number of man-hours may exceed the estimation. For those reasons, it is not unusual for the project to encounter the problem of insufficient time for development.
In view of the above, several techniques are proposed to improve the efficiency of verification tasks. For example, the following documents describe several techniques directed to extraction of test items for a specific verification step to reduce the time required for design and development.    U.S. Pat. No. 7,275,231    Japanese Laid-open Patent Publication No. 2006-85710    Japanese Laid-open Patent Publication No. 2004-185592    Japanese Laid-open Patent Publication No. 2007-257291
The extracted test items are then subjected to a verification process. However, testing them in a random order is not efficient at all because, if a desired test was placed in a later part of the verification process, it would take a long time for the user to receive an error report from that test. While the verification process includes a significant number of test steps, the scheduling of those steps depends on the expertise of users (i.e., design engineers and test engineers). They choose an appropriate verification procedure to prioritize their desired tests. Inexperienced engineers, however, lack this expertise for efficient verification, thus failing to choose a correct sequence of test steps.